24-bit, fixed point, 45 mips dsp core large on-board program ram and data ram (16kw-24 bit data ram and 16kw-24 bit program ram) integrated stereo, 16-bit sigma- delta a/d and d/a converters programmable codec sample rate from 4 to 48 khz on-board pll for core clock and converters management of external flash / sram / dram memory bank i 2 c or spi serial interface for ex- ternal control 80-pin tqfp, 0.65 mm pitch automotive grade (from -40 c to +85c) description the TDA7550R is a high performances, fully pro- grammable 24-bit, 45 mips digital signal proces- sor (dsp), designed to support several speech and audio applications, as automatic speech recognition, speech synthesis, speaker verifica- tion, echo and noise cancellation. software for these applications is licenced by lernout & haus- pie and bit innovation technologies. it offers an effective solution for this kind of appli- cations because of the a/d and d/a converters and the big amount of memory integrated on chip. applications real time digital speech and audio processing: speech recognition, speech synthesis, speech compression, echo canceling, noise canceling, speaker verification. july 2001 ? i 2 c/spi port gpios 8 memory interface sai program ram dsp core pll data ram analog out multiplexed bus analog in d99au1020b dac adc l r l r block diagram tqfp80 ordering number: TDA7550R TDA7550R digital signal processing ic for speech and audio applications 1/10
absolute maximum ratings symbol parameter value unit vdd 3.3v power supply voltage -0.5 to 4 v input or output voltage -0.5 to (vdd +0.5v) v input or output voltage (note 1) -0.5 to 5.5 v note 1: for 5v tolerant inputs and 5v tolerant output buffers in tri-state mode. thermal data symbol parameter value unit r th j-pins thermal resistance junction pins max. 55 c/w 1 2 3 5 6 4 7 8 9 10 31 11 32 33 34 35 36 75 74 73 72 70 71 69 68 67 66 65 55 54 53 51 50 52 60 59 58 56 57 emi_a8 emi_ad7 gnd emi_ad6 emi_ad5 vdd emi_a13 emi_a12 emi_a11 emi_a7 emi_a10 mosi vdd gnd test3 sck sdi lrck vdd gnd sdo gpio1 drdn gnd ale xto pgnd pvcc xti clkout vdd gpio4 gpio7 voutl voutr vdd gpio3 gpio6 gnd cgnda vinl vinr cvdd cgnd tqfp80 26 27 28 29 30 76 emi_ad0 77 emi_ad1 78 emi_ad2 79 emi_ad3 80 emi_ad4 emi_a21 dwrn test1 test2 miso 21 22 23 24 25 49 48 46 45 47 gpio2 gnd sda/ss scl/sck vdd 12 13 14 15 16 emi_a16 gnd vdd emi_a14 emi_a15 64 63 62 61 refcap vref cvdda test4 37 38 39 40 gpio0 gpio5 dbck dbin 44 42 41 43 intn dbrqn dbout nreset 17 18 19 20 emi_a20 emi_a19 emi_a18 emi_a17 pin connection TDA7550R 2/10
pin functions n. name type description 1 emi_ad5 i/o emi multiplexed address/data line 5. these pin acts as the emi multiplexed address and data line 5. in dram mode acts as address 1. 2 emi_ad6 i/o emi multiplexed address/data line 6. these pin acts as the emi multiplexed address and data line 6. in dram mode acts as address 2. 3 vdd i digital power supply 4 gnd i ground 5 emi_ad7 i/o emi multiplexed address/data line 7. these pin acts as the emi multiplexed address and data line 7. in dram mode acts as address 3. 6 emi_a8 o emi address line 8. these pin acts as the emi address line 8. the interface is designed to address up to 4 mbytes of external flash, eprom or sram. in dram mode acts as address 4. 7 emi_a9 o emi address line 9. these pin acts as the emi address line 9. in dram mode acts as address 5. 8 emi_a10 o emi address line 10. these pin acts as the emi address line 10. in dram mode acts as address 6. 9 emi_a11 o emi address line 11. these pin acts as the emi address line 11. in dram mode acts as address 7. 10 emi_a12 o emi address line 12. these pin acts as the emi address line 12. in dram mode acts as address 8. 11 emi_a13 o emi address line 13. these pin acts as the emi address line 13. in dram mode acts as address 9. 12 emi_a14 o emi address line 14. these pin acts as the emi address line 14. in dram mode acts as address 10. 13 emi_a15 o emi address line 15. these pin acts as the emi address line 15. in dram mode acts as address 11. 14 vdd i digital power supply 15 gnd i ground 16 emi_a16 o emi address line 16. these pin acts as the emi address line 16. in dram mode acts as address 12. 17 emi_a17 o emi address line 17. these pin acts as the emi address line 17. 18 emi_a18 o emi address line 18. these pin acts as the emi address line 18. 19 emi_a19 o emi address line 19. these pin acts as the emi address line 19. 20 emi_a20 o emi address line 20. these pin acts as the emi address line 20. 21 emi_a21 o emi address line 21. these pin acts as the emi address line 21. in dram mode acts as row address strobe. 22 dwrn o emi write enable. this pin serves as the write enable for the emi 23 test1 i test 1. used for test: set to low for normal operation 24 test2 i test 2. used for test: set to high for normal operation 25 miso i/o spi master input slave output serial data. serial data input for spi type serial port when in spi master mode and serial data output when in spi slave mode 26 mosi i/o spi master output slave input serial data. serial data output for spi type serial port when in spi master mode and serial data input when in spi slave mode 27 vdd i digital power supply 28 gnd i ground 29 test3 i test 3. used for test: set to low for normal operation 30 sdi i sai data input 31 sck i/o sai bit clock 32 lrck i/o sai left/right clock TDA7550R 3/10
n. name type description 33 vdd i digital power supply 34 gnd i ground 35 sdo o sai data output 36 gpio1 i/o general purpose i/o 37 gpio0 i/o general purpose i/o 38 gpio5 i/o general purpose i/o 39 dbck i/o debug port bit clock/chip status 1. the serial clock for the debug port is provided. may also be used as gpio9. 40 dbin i/o debug port serial input/chip status 0. the serial data input for the debug port is provided. may also be used as gpio11. 41 dbout i/o debug port serial output. this pin is the serial data output for the debug port. may also be used as gpio10. 42 dbrqn i debug port request input. this pin is used to request debug mode operation to euterpe 43 nreset i system reset. a low level applied to reset input initializes the ic. 44 intn i external interrupt line. when this line is asserted low the dsp may be interrupted. 45 scl/sck i/o i 2 c serial clock line. clock line for i 2 c bus. schmitt trigger input. i/o spi bit clock. if spi interface is enabled, it behaves as spi bit clock. 46 sda/ss i/o i 2 c serial data line. data line for i 2 c bus. schmitt trigger input. i spi slave select. if spi interface is enabled, it behaves as slave select line for spi bus. 47 vdd i digital power supply 48 gnd i ground 49 gpio2 i/o general purpose i/o 50 gpio6 i/o general purpose i/o 51 gpio3 i/o general purpose i/o 52 gnd i ground 53 vdd i digital power supply 54 voutr o single-ended right channel analogue output from dac 55 voutl o single-ended left channel analogue output from dac 56 cvdd i digital power supply for the internal codec cell 57 cgnd i ground for the internal codec cell 58 vinr i single-ended right channel analogue input to adc 59 vinl i single-ended left channel analogue input to adc 60 cgnda i ground for the internal codec cell 61 test4 o connect a 22k pull-down resistor 62 cvdda i power supply for the internal codec cell 63 vref o voltage reference from the codec cell 64 refcap o voltage reference capacitor bypass 65 gpio7 i/o general purpose i/o 66 gpio4 i/o general purpose i/o 67 vdd i digital power supply 68 clkout o clock output. output clock divided down from pll 69 xti i crystal oscillator input. crystal oscillator input drive pin functions (continued) TDA7550R 4/10
n. name type description 70 pgnd i pll ground input. ground connection for oscillator circuit 71 pvcc i pll power supply positive. supply for pll clock oscillator 72 xto o crystal oscillator output. crystal oscillator output drive 73 ale o emi address latch enable. this pin acts as the emi address latch enable for the external memory interface. in dram mode acts as column address strobe. 74 gnd i ground 75 drdn o emi read enable. this pin serves as the read enable for the emi 76 emi_ad0 i/o emi multiplexed address/data line 0. these pin acts as the emi multiplexed address and data line 0 in dram mode acts as data 0. 77 emi_ad1 i/o emi multiplexed address/data line 1. these pin acts as the emi multiplexed address and data line 1 in dram mode acts as data 1. 78 emi_ad2 i/o emi multiplexed address/data line 2. these pin acts as the emi multiplexed address and data line 2 in dram mode acts as data 2. 79 emi_ad3 i/o emi multiplexed address/data line 3. these pin acts as the emi multiplexed address and data line 3. in dram mode acts as data 3. 80 emi_ad4 i/o emi multiplexed address/data line 4. these pin acts as the emi multiplexed address and data line 4. in dram mode acts as address 0. all digital pins are ttl schmitt trigger, 5v tolerant. key parameters table 1. symbol parameter min. typ. max. unit general f osc crystal frequency 40 mhz v dd operating voltage 3.15 3.3 3.6 v i dd supply current 140 230 ma t amb operating temperature -40 85 c dsp core f dsp dsp clock frequency 45 48.2 mhz data bus width 24 bit accumulator width 56 bit multiplication unit 24x24 bit codec snr signal to noise ratio adc -70 dbr a weighted snr signal to noise ratio dac -71 dbr a weighted pin functions (continued) power dissipation power consumption depends on application run- ning and dsp clock frequency. medium consumption running a typical applica- tion like echo and noise cancellation: dsp clock freq. = 43mhz v = 3.3 idd = 145ma ptot = 478mw max consumption with high stress test program: dsp clock freq. = 43mhz v = 3.3 idd = 230ma ptot = 759mw TDA7550R 5/10
electrical characteristics for i/o pins: table 2. recommended dc operating conditions symbol parameter value unit vdd power supply voltage 3.15 to 3.6 (*) v tj operating junction temperature -40 to +125 c (*) all the specifications are valid only within these recommended operating conditions. table 3. general interface electrical characteristics symbol parameter test condition min. typ. max. unit iil low level input current without pullup device 1) vi = 0v 1 m a iih high level input current without pulldown device 1) vi = vdd 1 m a ioz tri-state output leakage without pull up/down device 1) vo = 0v or vdd 1 m a iozft five volt tolerant tri-state output leakage without pull up/down device 1) vo = 0v or vdd 1 m a vo = 5.5v 1 3 m a i latchup i/o latch-up current v < 0v, v < vdd 200 ma vesd electrostatic protection 2) leakage < 1 m a 2000 v note 1. the leakage currents are generally are generally very small, <1na. the value given here, 1ma, is a maximum that can occ ur after an electrostatic stress on the pin. note 2. human body model. table 4. low voltage ttl interface dc electrical characteristics symbol parameter test condition min. typ. max. unit vil low level input voltage 1) 0.8 v vih high level input voltage 1) 2v vilhyst low level threshold input falling 1) 0.9 1.35 v vihhyst high level threshold input falling 1) 1.3 1.9 v vhyst schmitt trigger hysteresis 1) 0.4 0.7 v vol low level output voltage 1),2),3) iol = xma 0.4 v voh high level output voltage 1),2),3) iol = xma 2.4 v note 1. ttl specifications only apply to the supply voltage range vdd = 3.15v to 3.6v. note 2. takes into account 200mv voltagedrop in both supply lines. note 3. x is the source/sink current under worst case conditions and is reflected in the name of the i/o cell according to the drive capability. TDA7550R 6/10
24 bit dsp core the dsp core is a general purpose 24-bit dsp. the main feature of the dsp core are listed be- low: 45mhz operating frequency (45 mips) single cycle multiply and accumulate 2x56-bit accumulators double precision multiply convergent rounding scaling and saturation arithmetic 48-bit or 2x24-bit parallel moves 21 programmable interrupt sources fast or long interrupts possible programmable interrupt priorities and masking 8 each address registers, address offset registers and address modulo registers linear, reverse carry, multiple buffer modulo, multiple wrap-around modulo address arith- metic post-increment or decrement by 1 or by offset, index by offset, predecrement address repeat instruction and zero overhead do loops hardware stackcapable of nesting 7 do loops or 15 interrupts/subroutines bit manipulation instructions possible on all registers and memory locations. also jump on bit test. data arithmetic logic unit (dalu) address generation unit (agu) program control unit (pcu) three data buses three address buses internal data bus switch bit manipulation unit debug logic memories 16384x24-bit program ram used for storing the program code. 16384x24-bit total data ram used for storing data. dsp peripherals serial audio interface (sai) the sai is used to deliver digital audio to the dsp from an external source and to deliver digital audio from the dsp to an external dac. it allows using an external codec. the main features of this block are listed below: C one data transmission line C one data reception line C master and slave operating modes C reference clock for transmission supplied C transmit and receive interrupt logic modified to trigger on left/right data pairs C receive and transmit data registers have two locations to hold left and right data i 2 c interface/spi the inter integrated-circuit bus is a simple bi-di- rectional two-wire bus used for efficient inter ic control. all i 2 c bus compatible devices incorpo- rate an on-chip interface which allows them communicate directly with each via the i 2 c bus. every component hoocked up to the i 2 c bus has its own unique address whether it is a cpu, memory or some other complex function chip. each of these chips can act as a receiver and/or transmitter depending on its functionality. the serial peripheral interface (spi) can be enabled instead of the i 2 c interface. during an spi transfer, data is trasmitted and received simulaneously. a serial clock line synchronizes shifting and sampling of the information on the two serial data lines. a slave select line allows individual selection of a slave spi device. when an spi transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin. the central element in the spi sys- tem is the shift register and the read data buff- er. the system is single buffered in the trasmit direction and double buffered in the receive di- rection. emi the external memory interface is viewed as a memory mapped peripheral. data transfers are performed by moving data into/from data regis- ters and the control is exercised by polling status flags in the control/status register or by servicing interrupts. an external memory write is executed by writing data into the data write register. an external memory read operation is executed by either writing to the offset register or reading the data read register, depending on the configuration. the main features of the emi are listed below: C data bus width fixed at 4 bits for dram and 8 bits for sram C 22 bit address bus multiplexed with an 8 bit data bus C three choices of data word lenghths, 8, 16 or 24 bits C sram relative addressing modes C 2 22 =4mbytes addressable sram C four sram timing choices TDA7550R 7/10
C two read offset register pll the euterpe clock system generates the fol- lowing clocks: C dclk the dsp core clock C mclk codec master clock C lrclk left/right clock for the sai and the codec C sclk shift serial clock for the sai and the codec the output of the pll operates from 70 to 140 mhz. the dsp core can operate with a clock up to 48.2 mhz. the audio clock are derived from the vco out- put. codec cell the main features of the codec cell are listed below: C one 16-bit delta sigma stereo adc C 80 db dynamic range C oversampling ratio: 128 C one 16-bit delta sigma stereo dac C 80 db dynamic range C interpolating ratio: 128 C sampling rates of 4khz to 48khz C signal noise ratio: 80 db typ. the analog interface is in the form of differen- tial signals for each channel. the interface on the digital side has the form of an sai interface and can interface directly to an sai channel and then to the dsp core. TDA7550R 8/10
dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.22 0.32 0.38 0.009 0.013 0.015 c 0.09 0.20 0.003 0.008 d 16.00 0.630 d1 14.00 0.551 d3 12.35 0.295 e 0.65 0.0256 e 16.00 0.630 e1 14.00 0.551 e3 12.35 0.486 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.0393 k3.5 (min.), 7 (max.) tqfp80 (14x14x1.40mm) a a2 a1 seating plane c 20 21 40 41 60 61 80 e3 d3 e1 e d1 d e 1 b tqfp80l 0.10mm .004 pin 1 identification k l l1 0.25mm gage plane outline and mechanical data TDA7550R 9/10
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com TDA7550R 10/10
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